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this document is a general product descripti on and is subject to change without notice. hynix semiconductor does not assume any responsibility for use of circuits described. no pat ent licenses are implied. rev. 0.3 / oct. 2008 1 240pin registered ddr2 sdram dimms based on 1gb version e this hynix registered dual in-l ine memory module (dimm) series consists of 1gb version e ddr2 sdrams in fine ball grid array (f bga) packages on a 240pin glass-epoxy substrate. this hynix 1gb version e based registered ddr2 dimm series provide a high performance 8 byte interface in 5.25" width form factor of industry standard. it is suitable for easy interchange and addition. features ordering information part name density organization # of drams # of ranks materials parity support hmp112p7efr8c-c4/y5/s6/s5 1gb 128mx72 9 1 halogen free o HMP125P7EFR8C-C4/y5/s6/s5 2gb 256mx72 18 2 halogen free o hmp125p7efr4c-c4/y5/s6/s5 2gb 256mx72 18 1 halogen free o hmp151p7efr8c-c4/y5/s6/s5 4gb 512mx72 36 4 halogen free o hmp151p7efr4c-c4/y5/s6/s5 4gb 512mx72 36 2 halogen free o hmp31gp7emr4c-c4/y5 8gb 512mx72 72 4 halogen free o ? jedec standard double data rate2 synchro- nous drams (ddr2 sdrams) with 1.8v +/- 0.1v power supply ? all inputs and outputs are compatible with sstl_1.8 interface ?8 bank architecture ?posted cas ? programmable cas latency 3, 4, 5, 6 ? ocd (off-chip driver impedance adjustment) ? odt (on-die termination) ? fully differential clock operations (ck & ck) ? programmable burst length 4 / 8 with both sequential and interleave mode ? auto refresh and self refresh supported ? 8192 refresh cycles / 64ms ? serial presence detect with eeprom ? ddr2 sdram package: 60 ball(x4/x8) ? 133.35 x 30.00 mm form factor ? halogen free & rohs compliant
rev. 0.3 / oct. 2008 2 1 240pin registered ddr2 sdram dimms speed grade & key parameters address table c4 (ddr2-533) y5 (ddr2-667) s6 (ddr2-800) s5 (ddr2-800) unit speed@cl3 400 400 - 400 mbps speed@cl4 533 533 533 533 mbps speed@cl5 - 667 667 800 mbps speed@cl6 - - 800 - mbps cl-trcd-trp 4-4-4 5-5-5 6-6-6 5-5-5 tck density organization ranks sdrams # of drams # of row/bank/column address refresh method 1gb 128m x 72 1 128mb x 8 9 14(a0~a13)/3(ba0~ba2)/10(a0~a9) 8k / 64ms 2gb 256m x 72 2 128mb x 8 18 14(a0~a13)/3(ba0~ba2)/10(a0~a9) 8k / 64ms 2gb 256m x 72 1 256mb x 4 18 14(a0~a13)/3(ba0~ba2)/11(a0~a9,a11) 8k / 64ms 4gb 512m x 72 4 128mb x 8 36 14(a0~a13)/3(ba0~ba2)/10(a0~a9) 8k / 64ms 4gb 512m x 72 2 256mb x 4 36 14(a0~a13)/3(ba0~ba2)/11(a0~a9,a11) 8k / 64ms 8gb 1g x 72 4 256mb x 4 72 14(a0~a13)/3(ba0~ba2)/11(a0~a9,a11) 8k / 64ms
rev. 0.3 / oct. 2008 3 1 240pin registered ddr2 sdram dimms input/output functional description symbol type polarity pin description ck0 in positive edge positive line of the differential pair of system clock inputs that drives input to the on-dimm pll. ck 0in negative edge negative line of the differential pair of system clock inputs that drives input to the on-dimm pll. cke[1:0] in active high activates the ddr2 sdram ck signal when high and deactivates the ck signal when low. by deactivat- ing the clocks, cke low initiates the power down mode or the self refresh mode. s [1:0] in active low enables the associated ddr2 sdram command decoder when low and disables the command decoder when high. when the command decoder is di sabled, new commands are ignored but previous operations continue. rank 0 is selected by s 0; rank 1 is selected by s 1 odt[1:0] in active high on-die termination signals. ras , cas , we in active low when sampled at the positive rising edge of the clock. ras ,cas and we (along with s) define the command being entered. vref supply reference voltage for sstl18 inputs v ddq supply power supplies for the ddr2 sdram output buffers to provide improved noise immunity. for all current ddr2 unbuffered dimm designs, v ddq shares the same power plane as v dd pins. ba[2:0] in - selects which ddr2 sdram internal bank of eight is activated. a[9:0],a10/ap a[13:11] in - during a bank activate command cycle, address input difines the row address(ra0~ra13) during a read or write command cycle, address input defines the column address when sampled at the cross point of the rising edge of ck and falling edge of ck . in addition to the column address, ap is used to invoke autoprecharge operation at the end of the burst read or write cycle. if ap is high., autopre- charge is selected and ba0-ban defines the bank to be precharged. if ap is lo w, autoprecharge is dis- abled. during a precharge command cycle., ap is us ed in conjunction with ba0-ban to control which bank(s) to precharge. if ap is high, all banks will be precharged regardless of the state of ba0-ban inputs. if ap is low, then ba0-ban ar e used to define which bank to precharge. dq[63:0], cb[7:0] in - data and check bit input/output pins. dm[8:0] in active high dm is an input mask signal for write data. input data is masked when dm is sampled high coincident with that input data during a write access. dm is sampled on both edges of dqs. although dm pins are input only, the dm loading matches the dq and dqs loading. v dd ,v ss supply power and ground for the ddr2 sdram input buffers, and core logic. v dd and v ddq pins are tied to v dd /v ddq planes on these modules. dqs[17:0] i o positive edge positive line of the differential data strobe for input and output data dqs[ 17:0] i o negative edge negative line of the differential data strobe for input and output data sa[2:0] in - these signals are tied at the system planar to either v ss or v ddspd to configure the serial spd eeprom address range. sda i/o - this is a bidirectional pin used to transfer data into or out of the spd eeprom. a resister may be con- nected from the sda bus line to v ddspd on the system planar to act as a pull up. scl in - this signal is used to clock data into and out of the spd eeprom. a resistor may be connected from scl to v ddspd to act as a pull up on the system board. vddspd supply power supply for spd eeprom. this supply is sepa rate from the vdd/vddq power plane. eeprom supply is operable from 1.7v to 3.6v. reset in the reset pin is connected to the rst pin on the register and to the oe pin on the pll. when low, all register outputs will be driven low and the pll clocks to the drams and register(s) will be set to low level (the pll will remain synchronized with the input clock) par_in in parity bit for the address and control bus(?1?. odd, ?0?.even) err_out out parity error found in the address and control bus test used by memory bus analysis tools (unused on memory dimms)
rev. 0.3 / oct. 2008 4 1 240pin registered ddr2 sdram dimms pin description pin location pin pin description pin pin description ck0 clock input, positive line odt[1:0] on die termination inputs ck 0 clock input, negative line vddq dqs power supply cke0~cke1 clock enable input dq0~dq63 data input/output ras row address strobe cb0~cb7 data check bits input/output cas column address strobe dqs(0~8) data strobes we write enable dqs (0~8) data strobes, negative line s 0,s 1 chip select input dm(0~8),dqs(9~17) data maskes/data strobes a0~a9,a11~a13 address input dqs(9~17) data strobes, negative line a10/ap address input/autoprecharge rfu reserved for future use ba0, ba1, ba2 sdram bank address nc no connect scl serial presence detect (spd) clock input test memory bus test tool (not connected and not usable on dimms) sda spd data input/output vdd core power sa0~sa2 e 2 prom address inputs vddq i/o power supply par_in parity bit for the address and control bus vss ground err_out parity error found on the address vref reference power supply reset reset enable vddspd power supply for spd cb0~cb7 data strobe inputs/outputs pin #1 front side pin #64 pin #65 pin #120 pin #121 back side pin #184 pin #185 pin #240
rev. 0.3 / oct. 2008 5 1 240pin registered ddr2 sdram dimms pin assignment nc= no connect, rfu= reserved for future use. note: 1. reset (pin 18) is connected to both oe of pll and reset of register. 2. nc/err_out (pin 55) and nc/par_in(pin68) are for optional function to check address and command parity. 3. the test pin (pin 102) is reserved for bus analysis probes and is not connected on normal memory modules (dimms) pin name pin name pin name pin name pin name pin name 1 vref 41 vss 81 dq33 121 vss 161 cb4 201 vss 2 vss 42 cb0 82 vss 122 dq4 162 cb5 202 dm4/dqs13 3 dq0 43 cb1 83 dqs 4 123 dq5 163 vss 203 dqs 13 4 dq1 44 vss 84 dqs4 124 vss 164 dm8,dqs17 204 vss 5 vss 45 dqs 8 85 vss 125 dm0/dqs9 165 dqs 17 205 dq38 6dqs 046dqs886 dq34126dqs 9 166 vss 206 dq39 7 dqs0 47 vss 87 dq35 127 vss 167 cb6 207 vss 8 vss 48 cb2 88 vss 128 dq6 168 cb7 208 dq44 9 dq2 49 cb3 89 dq40 129 dq7 169 vss 209 dq45 10 dq3 50 vss 90 dq41 130 vss 170 vddq 210 vss 11 vss 51 vddq 91 vss 131 dq12 171 nc,cke1 211 dm5/dqs14 12 dq8 52 cke0 92 dqs 5 132 dq13 172 vdd 212 dqs 14 13 dq9 53 vdd 93 dqs5 133 vss 173 a15,nc 213 vss 14 vss 54 ba2,nc 94 vss 134 dm1/dqs10 174 a14,nc 214 dq46 15 dqs 1 55 nc, err_out 95 dq42 135 dqs 10 175 vddq 215 dq47 16 dqs1 56 vddq 96 dq43 136 vss 176 a12 216 vss 17 vss 57 a11 97 vss 137 rfu 177 a9 217 dq52 18 reset 58 a7 98 dq48 138 rfu 178 vdd 218 dq53 19 nc 59 vdd 99 dq49 139 vss 179 a8 219 vss 20 vss 60 a5 100 vss 140 dq14 180 a6 220 rfu 21 dq10 61 a4 101 sa2 141 dq15 181 vddq 221 rfu 22 dq11 62 vddq 102 nc(test) 142 vss 182 a3 222 vss 23 vss 63 a2 103 vss 143 dq20 183 a1 223 dm6/dqs15 24 dq16 64 vdd 104 dqs 6 144 dq21 184 vdd 224 nc,dqs 15 25 dq17 key 105 dqs6 145 vss key 225 vss 26 vss 65 vss 106 vss 146 dm2/dqs11 185 ck0 226 dq54 27 dqs 2 66 vss 107 dq50 147 dqs 11 186 ck 0 227 dq55 28 dqs2 67 vdd 108 dq51 148 vss 187 vdd 228 vss 29 vss 68 nc, err_out 109 vss 149 dq22 188 a0 229 dq60 30 dq18 69 vdd 110 dq56 150 dq23 189 vdd 230 dq61 31 dq19 70 a10/ap 111 dq57 151 vss 190 ba1 231 vss 32 vss 71 ba0 112 vss 152 dq28 191 vddq 232 dm7/dqs16 33 dq24 72 vddq 113 dqs 7 153 dq29 192 ras 233 nc,dqs 16 34 dq25 73 we 114 dqs7 154 vss 193 s 0 234 vss 35 vss 74 cas 115 vss 155 dm3/dqs12 194 vddq 235 dq62 36 dqs 3 75 vddq 116 dq58 156 dqs 12 195 odt0 236 dq63 37 dqs3 76 nc, s 1 117 dq59 157 vss 196 a13,nc 237 vss 38 vss 77 nc, odt1 118 vss 158 dq30 197 vdd 238 vddspd 39 dq26 78 vddq 119 sda 159 dq31 198 vss 239 sa0 40 dq27 79 vss 120 scl 160 vss 199 dq36 240 sa1 80 dq32 200 dq37
rev. 0.3 / oct. 2008 6 1 240pin registered ddr2 sdram dimms functional block diagram 1gb(128mbx72): hmp112p7efr8c rs 0 -> cs : sdrams d0-d8 s 0* ba0-ba2** a0-a15** ras cas we cke0 odt1 reset pck7 pck 7 rba-rba2 -> ba0-ba2: sdrams d0-d8 ra0-ra15 -> a0-a15: sdrams d0-d8 rras -> ras : sdrams d0-d8 rcas -> cas : sdrams d0-d8 rwe -> we : sdrams d0-d8 rcke0 -> cke0: sdrams d0-d8 rodt0 -> odt0: sdrams d0-d8 1:2 r e g i s t e r rst serial pd wp a0 a1 a2 sa0 sa1 sa2 scl sda rs 0 dqs0 dq0 dq1 dq2 i/o 0 i/o 1 i/o 2 i/o 3 cs d0 dm/ dqs dqs dqs0 dq3 register par_in qerr par_in err_out k ? c1 c0 ppo v ss vss signals for address and command parity function the resistors on par_in,a13,a14,a15,ba2 and the signal line of err_out refer to the section: ?register options for unused address inputs? d0?d8 d0?d8 vref spd vdd/vddq v ss d0?d8 vddspd note: 1. dq-to-i/o wiring may be changed within a nibble. 2. unless otherwise noted, resistor values are 22 ohms ? 5%. * s 0 connects to dcs of vdd connects to csr on the register. s 1, cke1 and odt1 are nc. ** a13-15, ba2 have the optional pull down resistors (100k ohms), which is not indicated here. dq4 dq5 dq6 i/o 4 i/o 5 i/o 6 i/o 7 dq7 rdqs nu/ rdqs dm0/dqs9 dqs9 dqs4 dq32 dq33 dq33 i/o 0 i/o 1 i/o 2 i/o 3 cs d4 dm/ dqs dqs dqs4 dq34 dq35 dq36 dq37 i/o 4 i/o 5 i/o 6 i/o 7 dq38 rdqs nu/ rdqs dm4/dqs13 dqs13 dqs1 dq8 dq9 dq10 i/o 0 i/o 1 i/o 2 i/o 3 cs d1 dm/ dqs dqs dqs1 dq11 dq12 dq13 dq14 i/o 4 i/o 5 i/o 6 i/o 7 dq15 rdqs nu/ rdqs dm1/dqs10 dqs10 dqs5 dq40 dq41 dq42 i/o 0 i/o 1 i/o 2 i/o 3 cs d5 dm/ dqs dqs dqs5 dq43 dq44 dq45 dq46 i/o 4 i/o 5 i/o 6 i/o 7 dq47 rdqs nu/ rdqs dm5/dqs14 dqs14 pck7 -> ck: register pck 7 -> ck: register pck0-pck6, pck8, pck9 -> ck: sdrams d0-d8 pck 0-pck 6, pck 8, pck 9 -> ck : sdrams d0-d8 p l l ck0 ck 0 reset oe dqs2 dq16 dq17 dq18 i/o 0 i/o 1 i/o 2 i/o 3 cs d2 dm/ dqs dqs dqs2 dq19 dq20 dq21 dq22 i/o 4 i/o 5 i/o 6 i/o 7 dq23 rdqs nu/ rdqs dm2/dqs11 dqs11 dqs6 dq48 dq49 dq50 i/o 0 i/o 1 i/o 2 i/o 3 cs d6 dm/ dqs dqs dqs6 dq51 dq52 dq53 dq54 i/o 4 i/o 5 i/o 6 i/o 7 dq55 rdqs nu/ rdqs dm6/dqs15 dqs15 dqs3 dq24 dq25 dq26 i/o 0 i/o 1 i/o 2 i/o 3 cs d3 dm/ dqs dqs dqs3 dq27 dq28 dq29 dq30 i/o 4 i/o 5 i/o 6 i/o 7 dq31 rdqs nu/ rdqs dm3dqs12 dqs12 dqs7 dq56 dq57 dq58 i/o 0 i/o 1 i/o 2 i/o 3 cs d7 dm/ dqs dqs dqs7 dq59 dq60 dq61 dq62 i/o 4 i/o 5 i/o 6 i/o 7 dq63 rdqs nu/ rdqs dm7/dqs16 dqs16 dqs8 cb0 cb1 cb2 i/o 0 i/o 1 i/o 2 i/o 3 cs d8 dm/ dqs dqs dqs8 cb3 cb4 cb5 cb6 i/o 4 i/o 5 i/o 6 i/o 7 cb7 rdqs nu/ rdqs dm8/dqs17 dqs17
rev. 0.3 / oct. 2008 7 1 240pin registered ddr2 sdram dimms functional block diagram 2gb(256mbx72) : hmp125p7efr8c rs 1 -> cs : sdrams d9-d17 s 1* rs 0 -> cs : sdrams d0-d8 s 0* ba0-ba2*** a0-a15*** ras cas we cke0 odt1 reset** pck7** pck 7** rba0-rba2 -> ba0-ba2: sdrams d0-d17 ra0-ra15 -> a0-a15: sdrams d0-d17 rras -> ras : sdrams d0-d17 rcas -> cas : sdrams d0-d17 rwe -> we : sdrams d0-d17 rcke0 -> cke0: sdrams d0-d8 rodt1 -> odt0: sdrams d9-d17 1:2 r e g i s t e r rst serial pd wp a0 a1 a2 sa0 sa1 sa2 scl sda rs 0 dqs0 dq0 dq1 dq2 i/o 0 i/o 1 i/o 2 i/o 3 cs d0 dm/ dqs dqs dqs0 dq3 the resistors on par_in,a13,a14,a15,ba2 and the signal line of err_out refer to the section: ?register options for unused address inputs? d0?d17 d0?d17 vref spd vdd/vddq v ss d0?d17 vddspd * s 0 connects to dcs and s 1 connects to csr on registers. s 1 connects to dcs and s 0 connects to csr on another register. ** reset , pck7 and pck7 connect to both registers. other signals connect to one of two registers. *** a13-15, ba2 have the optional pull down resistors (100k ohms), which is not indicated here. dq4 dq5 dq6 i/o 4 i/o 5 i/o 6 i/o 7 dq7 rdqs nu/ rdqs dm0/dqs9 dqs9 i/o 0 i/o 1 i/o 2 i/o 3 cs d9 dm/ dqs dqs i/o 4 i/o 5 i/o 6 i/o 7 rdqs nu/ rdqs pck7 -> ck: register pck 7 -> ck: register pck0-pck6, pck8, pck9 -> ck: sdrams d0-d17 pck 0-pck 6, pck 8, pck 9 -> ck : sdrams d0-d17 p l l ck0 ck 0 reset oe rs 1 register a par_in qerr par_in err_out k ? c1 c0 ppo v dd vss signals for address and command parity function register b par_in qerr c1 c0 ppo v dd v dd dqs1 dq8 dq9 dq10 i/o 0 i/o 1 i/o 2 i/o 3 cs d1 dm/ dqs dqs dqs1 dq11 dq12 dq13 dq14 i/o 4 i/o 5 i/o 6 i/o 7 dq15 rdqs nu/ rdqs dm1/dqs10 dqs10 i/o 0 i/o 1 i/o 2 i/o 3 cs d10 dm/ dqs dqs i/o 4 i/o 5 i/o 6 i/o 7 rdqs nu/ rdqs dqs2 dq16 dq17 dq18 i/o 0 i/o 1 i/o 2 i/o 3 cs d2 dm/ dqs dqs dqs2 dq19 dq20 dq21 dq22 i/o 4 i/o 5 i/o 6 i/o 7 dq23 rdqs nu/ rdqs dm2/dqs11 dqs11 i/o 0 i/o 1 i/o 2 i/o 3 cs d11 dm/ dqs dqs i/o 4 i/o 5 i/o 6 i/o 7 rdqs nu/ rdqs dqs3 dq24 dq25 dq26 i/o 0 i/o 1 i/o 2 i/o 3 cs d3 dm/ dqs dqs dqs3 dq27 dq28 dq29 dq30 i/o 4 i/o 5 i/o 6 i/o 7 dq31 rdqs nu/ rdqs dm3/dqs12 dqs12 i/o 0 i/o 1 i/o 2 i/o 3 cs d12 dm/ dqs dqs i/o 4 i/o 5 i/o 6 i/o 7 rdqs nu/ rdqs dqs8 cb0 cb1 cb2 i/o 0 i/o 1 i/o 2 i/o 3 cs d8 dm/ dqs dqs dqs8 cb3 cb4 cb5 cb6 i/o 4 i/o 5 i/o 6 i/o 7 cb7 rdqs nu/ rdqs dm8dqs17 dqs17 i/o 0 i/o 1 i/o 2 i/o 3 cs d17 dm/ dqs dqs i/o 4 i/o 5 i/o 6 i/o 7 rdqs nu/ rdqs dqs4 dq32 dq33 dq34 i/o 0 i/o 1 i/o 2 i/o 3 cs d4 dm/ dqs dqs dqs4 dq35 dq36 dq37 dq38 i/o 4 i/o 5 i/o 6 i/o 7 dq39 rdqs nu/ rdqs dm4/dqs13 dqs13 i/o 0 i/o 1 i/o 2 i/o 3 cs d13 dm/ dqs dqs i/o 4 i/o 5 i/o 6 i/o 7 rdqs nu/ rdqs dqs5 dq40 dq41 dq42 i/o 0 i/o 1 i/o 2 i/o 3 cs d5 dm/ dqs dqs dqs5 dq43 dq40 dq41 dq42 i/o 4 i/o 5 i/o 6 i/o 7 dq43 rdqs nu/ rdqs dm5/dqs14 dqs14 i/o 0 i/o 1 i/o 2 i/o 3 cs d14 dm/ dqs dqs i/o 4 i/o 5 i/o 6 i/o 7 rdqs nu/ rdqs dqs6 dq48 dq49 dq50 i/o 0 i/o 1 i/o 2 i/o 3 cs d6 dm/ dqs dqs dqs6 dq51 dq52 dq53 dq54 i/o 4 i/o 5 i/o 6 i/o 7 dq55 rdqs nu/ rdqs dm6/dqs15 dqs15 i/o 0 i/o 1 i/o 2 i/o 3 cs d15 dm/ dqs dqs i/o 4 i/o 5 i/o 6 i/o 7 rdqs nu/ rdqs dqs7 dq56 dq57 dq58 i/o 0 i/o 1 i/o 2 i/o 3 cs d7 dm/ dqs dqs dqs7 dq59 dq60 dq61 dq62 i/o 4 i/o 5 i/o 6 i/o 7 dq63 rdqs nu/ rdqs dm7/dqs16 dqs16 i/o 0 i/o 1 i/o 2 i/o 3 cs d16 dm/ dqs dqs i/o 4 i/o 5 i/o 6 i/o 7 rdqs nu/ rdqs cke1 rcke1 -> cke0: sdrams d9-d17 r odt0 rodt0 -> odt0: sdrams d0-d8 note: 1. dq-to-i/o wiring may be changed within a byte. 2. unless otherwise noted, resistor values are 22 ohms ? 5%. 3. rs 0 and rs 1 alternate between the back and front sides of the dimm.
rev. 0.3 / oct. 2008 8 1 240pin registered ddr2 sdram dimms functional block diagram 2gb(256mbx72): hmp125p7efr4c rs 0 -> cs : sdrams d0-d17 s 0* ba0-ba2*** a0-a15*** ras cas we cke0 odt1 reset** pck7** pck 7** rba-rba2 -> ba0-ba2: sdrams d0-d17 ra0-ra15 -> a0-a15: sdrams d0-d17 rras -> ras : sdrams d0-d17 rcas -> cas : sdrams d0-d17 rwe -> we : sdrams d0-d17 rcke0 -> cke0: sdrams d0-d17 rodt0 -> odt0: sdrams d0-d17 1:2 r e g i s t e r rst serial pd wp a0 a1 a2 sa0 sa1 sa2 scl sda rs 0 dqs0 dq0 dq1 dq2 i/o 0 i/o 1 i/o 2 i/o 3 cs d0 dm dqs dqs dqs0 i/o 0 i/o 1 i/o 2 i/o 3 cs d9 dm dqs dqs dq3 dqs9 dqs9 dq4 dq5 dq6 dq7 vss dqs1 dq8 dq9 dq10 i/o 0 i/o 1 i/o 2 i/o 3 cs d1 dm dqs dqs dqs1 i/o 0 i/o 1 i/o 2 i/o 3 cs d10 dm dqs dqs dq11 dqs9 dqs9 dq12 dq13 dq14 dq15 dqs2 dq16 dq17 dq18 i/o 0 i/o 1 i/o 2 i/o 3 cs d2 dm dqs dqs dqs2 i/o 0 i/o 1 i/o 2 i/o 3 cs d11 dm dqs dqs dq19 dqs11 dqs11 dq20 dq21 dq22 dq23 dqs3 dq24 dq25 dq26 i/o 0 i/o 1 i/o 2 i/o 3 cs d3 dm dqs dqs dqs3 i/o 0 i/o 1 i/o 2 i/o 3 cs d12 dm dqs dqs dq27 dqs12 dqs12 dq28 dq29 dq30 dq31 dqs4 dq32 dq33 dq34 i/o 0 i/o 1 i/o 2 i/o 3 cs d4 dm dqs dqs dqs4 i/o 0 i/o 1 i/o 2 i/o 3 cs d13 dm dqs dqs dq35 dqs13 dqs13 dq36 dq37 dq38 dq39 dqs5 dq40 dq41 dq42 i/o 0 i/o 1 i/o 2 i/o 3 cs d5 dm dqs dqs dqs5 i/o 0 i/o 1 i/o 2 i/o 3 cs d14 dm dqs dqs dq43 dqs14 dqs14 dq44 dq45 dq46 dq47 dqs6 dq48 dq49 dq50 i/o 0 i/o 1 i/o 2 i/o 3 cs d6 dm dqs dqs dqs6 i/o 0 i/o 1 i/o 2 i/o 3 cs d15 dm dqs dqs dq51 dqs15 dqs15 dq52 dq53 dq54 dq55 dqs7 dq56 dq57 dq58 i/o 0 i/o 1 i/o 2 i/o 3 cs d7 dm dqs dqs dqs7 i/o 0 i/o 1 i/o 2 i/o 3 cs d16 dm dqs dqs dq59 dqs16 dqs16 dq60 dq61 dq62 dq63 dqs8 cb0 cb1 cb2 i/o 0 i/o 1 i/o 2 i/o 3 cs d8 dm dqs dqs dqs8 i/o 0 i/o 1 i/o 2 i/o 3 cs d17 dm dqs dqs cb3 dqs17 dqs17 cb4 cb5 cb6 cb7 register a par_in qerr par_in err_out k ? c1 c0 ppo v dd vss signals for address and command parity function register b par_in qerr c1 c0 ppo v dd v dd the resistors on par_in,a13,a14,a15,ba2 and the signal line of err_out refer to the section: ?register options for unused address inputs? d0?d17 d0?d17 vref spd vdd/vddq v ss d0?d17 vddspd note: 1. dq-to-i/o wiring may be changed within a nibble. 2. unless otherwise noted, resistor values are 22 ohms ? 5%. * s 0 connects to dcs of register a and csr of register b. csr of register a and dcs of register b connects to vdd. ** reset , pck7 and pck 7 connects to both registers. other signals connect to one of two registers. *** a13-15, ba2 have the optional pull down resistors (100k ohms), which is not indicated here. pck7 -> ck: register pck 7 -> ck: register pck0-pck6, pck8, pck9 -> ck: sdrams d0-d17 pck 0-pck 6, pck 8, pck 9 -> ck : sdrams d0-d17 p l l ck0 ck 0 reset oe
rev. 0.3 / oct. 2008 9 1 240pin registered ddr2 sdram dimms functional block diagram 4gb(512mbx72) : hmp151p7efr8c rdot0 rcke0 rs 0 dqs0 dqs 0 dq7-0 dm0 dqs dqs dq7-0 dm cs d0 cke odt dqs dqs dq7-0 dm cs d9 cke odt rs 1 dqs1 dqs 1 dq15-8 dm1 dqs dqs dq7-0 dm cs d1 cke odt dqs dqs dq7-0 dm cs d10 cke odt dqs2 dqs 2 dq23-16 dm2 dqs dqs dq7-0 dm cs d2 cke odt dqs dqs dq7-0 dm cs d11 cke odt dqs3 dqs 3 dq31-24 dm3 dqs dqs dq7-0 dm cs d3 cke odt dqs dqs dq7-0 dm cs d12 cke odt dqs4 dqs 4 cb7-0 dm8 dqs dqs dq7-0 dm cs d4 cke odt dqs dqs dq7-0 dm cs d13 cke odt dqs4 dqs 4 dq39-32 dm4 dqs dqs dq7-0 dm cs d5 cke odt dqs dqs dq7-0 dm cs d14 cke odt dqs5 dqs 5 dq47-40 dm5 dqs dqs dq7-0 dm cs d6 cke odt dqs dqs dq7-0 dm cs d15 cke odt dqs6 dqs 6 dq55-48 dm6 dqs dqs dq7-0 dm cs d7 cke odt dqs dqs dq7-0 dm cs d16 cke odt dqs7 dqs 7 dq63-56 dm7 dqs dqs dq7-0 dm cs d8 cke odt dqs dqs dq7-0 dm cs d17 cke odt rdot1 rcke1 rs 2 dqs dqs dq7-0 dm cs d18 cke odt dqs dqs dq7-0 dm cs d27 cke odt rs 3 dqs dqs dq7-0 dm cs d19 cke odt dqs dqs dq7-0 dm cs d28 cke odt dqs dqs dq7-0 dm cs d20 cke odt dqs dqs dq7-0 dm cs d29 cke odt dqs dqs dq7-0 dm cs d21 cke odt dqs dqs dq7-0 dm cs d30 cke odt dqs dqs dq7-0 dm cs d22 cke odt dqs dqs dq7-0 dm cs d31 cke odt dqs dqs dq7-0 dm cs d23 cke odt dqs dqs dq7-0 dm cs d32 cke odt dqs dqs dq7-0 dm cs d24 cke odt dqs dqs dq7-0 dm cs d33 cke odt dqs dqs dq7-0 dm cs d25 cke odt dqs dqs dq7-0 dm cs d34 cke odt dqs dqs dq7-0 dm cs d26 cke odt dqs dqs dq7-0 dm cs d35 cke odt serial pd wp a0 a1 a2 sa0 sa1 sa2 scl sda d0?d35 d0?d35 vref spd vdd/vddq v ss d0?d35 vddspd pck7 -> ck: register pck 7 -> ck: register pck0-pck6, pck8,pck9 pck 0-pck 6, pck 8, pck 9 p l l ck0 ck 0 reset oe -> ck: sdrams d0-d35 -> ck : sdrams d0-d35 rs 0 -> cs : sdrams d0-d8, rs 2 -> cs : sdrams d18-d26 s 0,s 2* s 1,s 3* ba0-ba2*** a0-a15*** ras cas we cke0 cke1 odt1 odt0 reset** pck7** pck 7** rs 1 -> cs : sdrams d9-d17,rs 3 -> cs : sdrams d27-d35 rba0-rba2 -> ba0-ba2: sdrams d0-d35**** ra0-ra15 -> a0-a15: sdrams d0-d35**** rras -> ras : sdrams d0-d35 rcas -> cas : sdrams d0-d35 rwe -> we : sdrams d0-d35 rcke0 -> cke: sdrams d0-d17 rcke1 -> cke: sdrams d18-d35 rodt0 -> odt0: sdrams d0-d8 rodt1 -> odt1: sdrams d18-d26 1:2 r e g i s t e r rst register a2 par_in qerr err_out c1 c0 ppo v dd vss signals for address and command register b2 par_in qerr c1 c0 ppo v dd v dd register a1 par_in qerr c1 c0 ppo v dd vss register b1 par_in qerr c1 c0 ppo v dd v dd parity function register a1 and a2 share the a part of addr/cmd input signal set. register b1 and b2 chare the rest part of addr/cmd input signal set. the resistors on par_in, a13, a14. a15,ba2 and the signal line of err_out refer to the section: the egister options for unused address inputs? * s 0 (s 2) connects to dcs 0, s1 (s 3) to dcs 1 on a register a. s 1 (s 3) connects to dcs and s 0 (s 2) connects to csr on another pair of register. * s 2 and s3 have required upll up resistors (100k ohms), not indicated here. ** reset , pck7 and pck 7 connect to all registers. other signals connect to two of four registers. *** a13-15, ba2 have the optional pull down resistors(100k ohms), which is not indicated here. **** for raw card n2, dq stub resistor value is tbd. and for raw card n2, post register a14 and a15 are not connected to the sdrams.
rev. 0.3 / oct. 2008 10 1 240pin registered ddr2 sdram dimms functional block diagram 4gb(512mbx72): hmp151p7efr4c vss rs 0 rs 1 dqs0 dq0 dq1 dq2 i/o 0 i/o 1 i/o 2 i/o 3 cs d18 rs 0 -> cs : sdrams d0-d17 s 0* s 1* ba0-ba2*** a0-a15*** ras cas we cke0 cke1 odt1 odt0 reset** pck7** pck 7** rs 1 -> cs : sdrams d18-d35 rba0-rba2 -> ba0-ba2: sdrams d0-d35 ra0-ra15 -> a0-a15: sdrams d0-d35 rras -> ras : sdrams d0-d35 rcas -> cas : sdrams d0-d35 rwe -> we : sdrams d0-d35 rcke0 -> cke0-1: sdrams d0-d17 rcke1 -> cke0-1: sdrams d18-d35 rodt0 -> odt1: sdrams d0-d17 rodt1 -> odt1: sdrams d18-d35 *s 0 connects to dcs and s 1 command to crs on a pair of register, s 2 connects to dcs and s 0 connect to crs on another pair of register. ** reset , pck7 and pck 7 connect to all registers. other signals connect to one pair of four registers. *** a14-15, ba2 have the optional pull down resist ors (100k ohms), which is not indicated here. 1:2 r e g i s t e r pck7 -> ck: register pck 7 -> ck: register pck0-pck6, pck8, pck9 -> ck: sdrams d0-d35 pck 0-pck 6, pck 8, pck 9 -> ck : sdrams d0-d35 p l l rst ck0 ck 0 reset oe register register parin ptyerr parin ptyerr par_in err_out serial pd wp a0 a1 a2 sa0 sa1 sa2 scl sda k ? ? dm dqs dqs i/o 0 i/o 1 i/o 2 i/o 3 cs d0 dm dqs dqs dqs0 i/o 0 i/o 1 i/o 2 i/o 3 cs d27 dm dqs dqs i/o 0 i/o 1 i/o 2 i/o 3 cs d9 dm dqs dqs dq3 dqs9 dqs9 dq4 dq5 dq6 dq7 dqs1 dq8 dq9 dq10 i/o 0 i/o 1 i/o 2 i/o 3 cs d19 dm dqs dqs i/o 0 i/o 1 i/o 2 i/o 3 cs d1 dm dqs dqs dqs1 i/o 0 i/o 1 i/o 2 i/o 3 cs d28 dm dqs dqs i/o 0 i/o 1 i/o 2 i/o 3 cs d10 dm dqs dqs dq11 dqs10 dqs10 dq12 dq13 dq14 dq15 dqs2 dq16 dq17 dq18 i/o 0 i/o 1 i/o 2 i/o 3 cs d20 dm dqs dqs i/o 0 i/o 1 i/o 2 i/o 3 cs d2 dm dqs dqs dqs2 i/o 0 i/o 1 i/o 2 i/o 3 cs d29 dm dqs dqs i/o 0 i/o 1 i/o 2 i/o 3 cs d11 dm dqs dqs dq19 dqs11 dqs11 dq20 dq21 dq22 dq23 dqs3 dq24 dq25 dq26 i/o 0 i/o 1 i/o 2 i/o 3 cs d21 dm dqs dqs i/o 0 i/o 1 i/o 2 i/o 3 cs d3 dm dqs dqs dqs3 i/o 0 i/o 1 i/o 2 i/o 3 cs d30 dm dqs dqs i/o 0 i/o 1 i/o 2 i/o 3 cs d12 dm dqs dqs dq27 dqs12 dqs12 dq28 dq29 dq30 dq30 dqs8 dqs17 rs 0 rs 1 dqs4 dq32 dq33 dq34 i/o 0 i/o 1 i/o 2 i/o 3 cs d22 dm dqs dqs i/o 0 i/o 1 i/o 2 i/o 3 cs d4 dm dqs dqs dqs4 i/o 0 i/o 1 i/o 2 i/o 3 cs d31 dm dqs dqs i/o 0 i/o 1 i/o 2 i/o 3 cs d13 dm dqs dqs dq35 dqs13 dqs13 dq36 dq37 dq38 dq39 dqs5 dq40 dq41 dq42 i/o 0 i/o 1 i/o 2 i/o 3 cs d23 dm dqs dqs i/o 0 i/o 1 i/o 2 i/o 3 cs d5 dm dqs dqs dqs5 i/o 0 i/o 1 i/o 2 i/o 3 cs d32 dm dqs dqs i/o 0 i/o 1 i/o 2 i/o 3 cs d14 dm dqs dqs dq43 dqs14 dqs14 dq44 dq45 dq46 dq47 dqs6 dq48 dq49 dq50 i/o 0 i/o 1 i/o 2 i/o 3 cs d24 dm dqs dqs i/o 0 i/o 1 i/o 2 i/o 3 cs d6 dm dqs dqs dqs6 i/o 0 i/o 1 i/o 2 i/o 3 cs d33 dm dqs dqs i/o 0 i/o 1 i/o 2 i/o 3 cs d15 dm dqs dqs dq51 dqs15 dqs15 dq52 dq53 dq54 dq55 dqs7 dq56 dq57 dq58 i/o 0 i/o 1 i/o 2 i/o 3 cs d25 dm dqs dqs i/o 0 i/o 1 i/o 2 i/o 3 cs d7 dm dqs dqs dqs7 i/o 0 i/o 1 i/o 2 i/o 3 cs d34 dm dqs dqs i/o 0 i/o 1 i/o 2 i/o 3 cs d16 dm dqs dqs dq59 dqs16 dqs16 dq60 dq61 dq62 dq63 note: 1. dq-to-i/o wiring may be changed within a nibble. 2. unless otherwise noted, resistor values are 22 ohms ? 5%. 3. rs0 and rs1 alternate between the bottom and surface sides of the dimm. cb0 cb1 cb2 i/o 0 i/o 1 i/o 2 i/o 3 cs d26 dm dqs dqs i/o 0 i/o 1 i/o 2 i/o 3 cs d8 dm dqs dqs dqs8 i/o 0 i/o 1 i/o 2 i/o 3 cs d35 dm dqs dqs i/o 0 i/o 1 i/o 2 i/o 3 cs d17 dm dqs dqs cb3 dqs17 cb4 cb5 cb6 cb7 signals for address and command parity function o ohm resistor on err_out is not populated for non-parity card. the resistors on par_in,a13,a14,a15,ba2 and the signal line of err_out refer to the section: ?register options for unused address input? d0?d35 d0?d35 vref spd vdd/vddq v ss d0?d35 vddspd
rev. 0.3 / oct. 2008 11 1 240pin registered ddr2 sdram dimms functional block diagram 8gb(1gbx72): hmp31gp7efr4c rodt0 rcke0 rs 1 rs 0 rodt1 rcke1 rs 3 rs 2 rodt0 rcke0 rs 1 rs 0 rodt1 rcke1 rs 3 rs 2 rodt0 rcke0 rs 1 rs 0 rodt1 rcke1 rs 3 rs 2 dqs dqs dq3~0 dm cs 0 cs 1 cke0 cke1 odt0 odt1 d0 dqs0 dqs0 dq3~0 rodt0 rcke0 rs 1 rs 0 rodt1 rcke1 rs 3 rs 2 dqs dqs dq3~0 dm cs 0 cs 1 cke0 cke1 odt0 odt1 d1 dqs dqs dq3~0 dm cs 0 cs 1 cke0 cke1 odt0 odt1 d2 dqs dqs dq3~0 dm cs 0 cs 1 cke0 cke1 odt0 odt1 d3 dqs dqs dq3~0 dm cs 0 cs 1 cke0 cke1 odt0 odt1 d8 dqs dqs dq3~0 dm cs 0 cs 1 cke0 cke1 odt0 odt1 d18 dqs dqs dq3~0 dm cs 0 cs 1 cke0 cke1 odt0 odt1 d19 dqs dqs dq3~0 dm cs 0 cs 1 cke0 cke1 odt0 odt1 d20 dqs dqs dq3~0 dm cs 0 cs 1 cke0 cke1 odt0 odt1 d21 dqs dqs dq3~0 dm cs 0 cs 1 cke0 cke1 odt0 odt1 d26 dqs dqs dq3~0 dm cs 0 cs 1 cke0 cke1 odt0 odt1 d9 dqs dqs dq3~0 dm cs 0 cs 1 cke0 cke1 odt0 odt1 d10 dqs dqs dq3~0 dm cs 0 cs 1 cke0 cke1 odt0 odt1 d11 dqs dqs dq3~0 dm cs 0 cs 1 cke0 cke1 odt0 odt1 d12 dqs dqs dq3~0 dm cs 0 cs 1 cke0 cke1 odt0 odt1 d17 dqs dqs dq3~0 dm cs 0 cs 1 cke0 cke1 odt0 odt1 d27 dqs dqs dq3~0 dm cs 0 cs 1 cke0 cke1 odt0 odt1 d28 dqs dqs dq3~0 dm cs 0 cs 1 cke0 cke1 odt0 odt1 d29 dqs dqs dq3~0 dm cs 0 cs 1 cke0 cke1 odt0 odt1 d35 dqs dqs dq3~0 dm cs 0 cs 1 cke0 cke1 odt0 odt1 d30 dqs dqs dq3~0 dm cs 0 cs 1 cke0 cke1 odt0 odt1 d4 dqs dqs dq3~0 dm cs 0 cs 1 cke0 cke1 odt0 odt1 d7 dqs dqs dq3~0 dm cs 0 cs 1 cke0 cke1 odt0 odt1 d22 dqs dqs dq3~0 dm cs 0 cs 1 cke0 cke1 odt0 odt1 d23 dqs dqs dq3~0 dm cs 0 cs 1 cke0 cke1 odt0 odt1 d24 dqs dqs dq3~0 dm cs 0 cs 1 cke0 cke1 odt0 odt1 d25 dqs dqs dq3~0 dm cs 0 cs 1 cke0 cke1 odt0 odt1 d13 dqs dqs dq3~0 dm cs 0 cs 1 cke0 cke1 odt0 odt1 d14 dqs dqs dq3~0 dm cs 0 cs 1 cke0 cke1 odt0 odt1 d15 dqs dqs dq3~0 dm cs 0 cs 1 cke0 cke1 odt0 odt1 d16 dqs dqs dq3~0 dm cs 0 cs 1 cke0 cke1 odt0 odt1 d31 dqs dqs dq3~0 dm cs 0 cs 1 cke0 cke1 odt0 odt1 d32 dqs dqs dq3~0 dm cs 0 cs 1 cke0 cke1 odt0 odt1 d33 dqs dqs dq3~0 dm cs 0 cs 1 cke0 cke1 odt0 odt1 d34 dqs dqs dq3~0 dm cs 0 cs 1 cke0 cke1 odt0 odt1 d5 dqs dqs dq3~0 dm cs 0 cs 1 cke0 cke1 odt0 odt1 d6 dqs1 dqs1 dq11~8 dqs2 dqs2 dq19~26 dqs3 dqs3 dq27~24 dqs8 dqs8 cb3~0 dqs9 dqs9 dq7~4 dqs10 dqs10 dq15~12 dqs11 dqs11 dq23~20 dqs12 dqs12 dq31~28 dqs17 dqs17 cb7~4 dqs4 dqs4 dq35~32 dqs5 dqs5 dq43~40 dqs dqs6 dq51~48 dqs7 dqs7 dq59~56 dqs13 dqs13 dq39~36 dqs14 dqs14 dq47~44 dqs15 dqs15 dq55~52 dqs16 dqs16 dq63~60 dqs dqs dq3~0 cs 0 cs 1 cke0 cke1 odt0 odt1 d0 dm rs 0 -> cs 0: sdrams d0-d17, rs 2 -> cs 0: sdrams d18-d35 s 0,2* s 1,3** ba0-ba2*** a0-a15*** ras cas we cke0 cke1 odt0 odt1 reset pck7 pck 7 rs 1 -> cs 1: sdrams d0-d17, rs 3 -> cs 1: sdrams d18-d35 rba-rba2 -> ba0-ba1: sdrams d0-d35 ra0-ra13 -> a0-a13: sdrams d0-d35 rras -> ras : sdrams d0-d35 rcas -> cas : sdrams d0-d35 rwe -> we : sdrams d0-d35 rcke0 -> cke0-1: sdrams d0-d17 rcke1 -> cke0-1: sdrams d18-d35 rodt0 -> odt1: sdrams d0-d17 rodt1 -> odt1: sdrams d18-d35 *s 0 connects to dcs 0, s 1 to dcs 1 on the first register, s 2 connects to dcs 0, s 3 to dcs 1 on the second register. ** s 2 and s 3 have required pull up resistors (100k ohms), not indicated here. *** a13-15, ba2 have optional pull down resistors (100k ohms), not indicated here. 1:2 r e g i s t e r pck7 -> ck: register pck 7 -> ck: register pck0-pck6, pck8, pck9 -> ck: sdrams d0-d35 pck 0-pck 6, pck 8, pck 9 -> ck : sdrams d0-d35 p l l rst ck0 ck 0 reset oe register register parin ptyerr parin ptyerr par_in err_out serial pd wp a0 a1 a2 sa0 sa1 sa2 scl sda k ? ? ? 22 ? 22 ? 22 ?
rev. 0.3 / oct. 2008 12 1 240pin registered ddr2 sdram dimms absolute maximum dc ratings operating conditions and environmental parameters note: 1. stress greater than those listed may cause permanent damage to the device. this is a st ress rating only, and device functional operation at or above t he conditions indicated is not implied. expousure to absolute maximum rating con ditions for extended periods may affect reliablility. 2. up to 9850 ft. 3. if the dram case temperature is above 85 o c, the auto-refresh command interval has to be reduced to trefi=3.9us. for measurement conditions of t case , please refer to the jedec document jesd51-2. dc operating conditions (sstl_1.8) note: 1. min. typ. and max. values increase by 100mv for c3(ddr2-533 3-3-3) speed option. 2. vddq tracks with vdd,vddl tracks with vdd. ac parameters are measured with vdd,vddq and vdd. 3. the value of vref may be selected by the user to provide optimum noise margin in the system. typically the value of vref is expected to be about 0.5 x vddq of t he transmitting device and vref is expected to track variations in vddq. 4. peak to peak ac noise on vref may not exceed +/-2% vref (dc). 5. vtt of transmitting device must track vref of receiving device. parameter symbol value unit note voltage on v dd pin relative to vss v dd - 1.0 ~ 2.3 v 1 voltage on v ddq pin relative to vss v ddq - 0.5 ~ 2.3 v 1 voltage on v ddl pin relative to vss v ddl - 0.5 ~ 2.3 v 1 voltage on any pin relative to vss v in, v out - 0.5 ~ 2.3 v 1 parameter symbol rating units notes dimm operating temperature (ambient) t opr 0 ~ +55 o c storage temperature t stg -50 ~ +100 o c 1 storage humidity (without condensation) h stg 5 to 95 % 1 dimm barometric pressure (operating & storage) p bar 105 to 69 k pascal 2 dram component case temperature range t case 0 ~+95 o c3 symbol parameter rating units notes min. typ. max. vdd supply voltage 1.7 1.8 1.9 v 1 vddl supply voltage for dll 1.7 1.8 1.9 v 1,2 vddq supply voltage for output 1.7 1.8 1.9 v 1,2 vref input reference voltage 0.49*vddq 0.50*vddq 0.51*vddq mv 3,4 vtt termination voltage vref-0.04 vref vref+0.04 v 5 vddspd eeprom supply voltage 1.7 - 3.6 v
rev. 0.3 / oct. 2008 13 1 240pin registered ddr2 sdram dimms input dc logic level input ac logic level ac input test conditions note : 1. input waveform timing is referenced to the input signal crossing through the v ref level applied to the device under test. 2. the input signal minimum slew rate is to be maintained over the range from v ref max to v ih(ac) min for rising edges and the range from v ref min to v il(ac) max for falling edges as shown in the below figure. 3. ac timings are referenced with input waveforms switching from vil (ac) to vih (ac) on the positive transitions and vih (ac) t o vil (ac) on the negative transitions. parameter symbol min max unit note dc input logic high v ih (dc) v ref + 0.125 v ddq + 0.3 v dc input logic low v il (dc) -0.30 v ref - 0.125 v parameter symbol ddr2 400/533 ddr2 667/800 unit notes min max min max ac input logic high v ih (ac) v ref + 0.250 - v ref + 0.200 - v ac input logic low v il (ac) -v ref - 0.250 - v ref - 0.200 v symbol condition value units notes v ref input reference voltage 0.5 * v ddq v1 v swing(max) input signal maximum peak to peak swing 1.0 v 1 slew input signal minimum slew rate 1.0 v/ns 2, 3 v ddq v ih(ac) min v ih(dc) min v ref v il(dc) max v il(ac) max v ss < figure: ac input test signal waveform > v swing(max) ? tr ? tf start of falling edge input timing start of rising edge input timing v ref - v il (ac) max ? tf falling slew = rising slew = v ih(ac) min - v ref ? tr
rev. 0.3 / oct. 2008 14 1 240pin registered ddr2 sdram dimms differential input ac logic level note: 1. v in (dc) specifies the allowable dc execution of each input of differential pair such as ck, ck , dqs, dqs , ldqs, ldqs , udqs and udqs . 2. v id (dc) specifies the input differential voltage |v tr -v cp | required for switching, where v tr is the true input (such as ck, dqs, ldqs or udqs) level and v cp is the complementary input (such as ck , dqs , ldqs or udqs ) level. the minimum value is equal to v ih (dc) - v il (dc). note : 1. v id (ac) specifies the input differential voltage |v tr -v cp | required for switching, where v tr is the true input signal (such as ck, dqs, ldqs or udqs) and v cp is the complementary input signal (such as ck , dqs , ldqs or udqs ). the minimum value is equal to v ih (ac) - v il (ac). 2. the typical value of v ix (ac) is expected to be about 0.5 * v ddq of the transmitting device and v ix (ac) is expected to track variations in v ddq . v ix (ac) indicates the voltage at which differential input signals must cross. differential ac output parameters note: 1. the typical value of v ox (ac) is expected to be about 0.5 * v ddq of the transmitting device and v ox (ac) is expected to track variations in v ddq . v ox (ac) indicates the voltage at which differential output signals must cross. symbol parameter min. max. units note v id (ac) ac differential input voltage 0.5 v ddq + 0.6 v 1 v ix (ac) ac differential cross point voltage 0.5 * v ddq - 0.175 0.5 * v ddq + 0.175 v 2 symbol parameter min. max. units note v ox (ac) ac differential crosspoint voltage 0.5 * v ddq - 0.125 0.5 * v ddq + 0.125 v 1 v ddq crossing point v ssq v tr v cp v id v ix or v ox < differential signal levels >
rev. 0.3 / oct. 2008 15 1 240pin registered ddr2 sdram dimms output buffer levels output ac test conditions note: 1. the vddq of the device under test is referenced. output dc current drive note: 1.v ddq = 1.7 v; v out = 1420 mv. (v out - v ddq )/i oh must be less than 21 ohm for values of v out between v ddq and v ddq - 280 mv. 2. v ddq = 1.7 v; v out = 280 mv. v out /i ol must be less than 21 ohm for values of v out between 0 v and 280 mv. 3. the dc value of v ref applied to the receiving device is set to v tt 4. the values of i oh (dc) and i ol (dc) are based on the conditions given in notes 1 and 2. they are used to test device drive current capa- bility to ensure v ih min plus a noise margin and v il max minus a noise margin are delivered to an sstl_18 receiver. the actual cur- rent values are derived by shifting the desired driver operating point along a 21 ohm l oad line to define a convenient driver c urrent for measurement. symbol parameter sstl_18 units notes v otr output timing measurement reference level 0.5 * v ddq v1 symbol parameter sstl_18 units notes i oh(dc) output minimum source dc current - 13.4 ma 1, 3, 4 i ol(dc) output minimum sink dc current 13.4 ma 2, 3, 4
rev. 0.3 / oct. 2008 16 1 240pin registered ddr2 sdram dimms pin capacitance (vdd=1.8v,vddq=1.8v, ta=25c) 1gb: hmp112p7efr8c 2gb: hmp125p7efr8c 2gb: hmp125p7efr4c 4gb: hmp151p7efr8c pin symbol min max unit ck0, /ck 0cck711 pf cke, odt ci1 8 12 pf /cs ci2 8 12 pf address, /ras , /cas , /we ci3 8 12 pf dq, dm, dqs, /dqs cio 6 9 pf pin symbol min max unit ck0, /ck 0cck711 pf cke, odt ci1 8 12 pf /cs ci2 10 15 pf address, /ras , /cas , /we ci3 8 12 pf dq, dm, dqs, /dqs cio 6 9 pf pin symbol min max unit ck0, /ck 0cck711 pf cke, odt ci1 8 12 pf /cs ci2 10 15 pf address, /ras , /cas , /we ci3 8 12 pf dq, dm, dqs, /dqs cio 6 9 pf pin symbol min max unit ck0, /ck 0cck711 pf cke, odt ci1 10 15 pf /cs ci2 10 15 pf address, /ras , /cas , /we ci3 10 15 pf dq, dm, dqs, /dqs cio 9 15 pf
rev. 0.3 / oct. 2008 17 1 240pin registered ddr2 sdram dimms 4gb: hmp151p7efr4c 8gb: hmp31gp7emr4c note: 1. pins not under test are tied to gnd. 2. these value are guaranteed by design and tested on a sample basis only. pin symbol min max unit ck0, /ck 0cck711 pf cke, odt ci1 10 15 pf /cs ci2 10 15 pf address, /ras , /cas , /we ci3 10 15 pf dq, dm, dqs, /dqs cio 9 15 pf pin symbol min max unit ck0, /ck 0cck711 pf cke, odt ci1 8 12 pf /cs ci2 8 12 pf address, /ras , /cas , /we ci3 10 15 pf dq, dm, dqs, /dqs cio 18 22 pf
rev. 0.3 / oct. 2008 18 1 240pin registered ddr2 sdram dimms idd specifications (t case : 0 to 95 o c) 1gb, 128m x 72 registered dimm : hmp112p7efr8c 2gb, 256m x 72 registered dimm : hmp125p7efr8c symbol c4 (ddr2 533@cl4) y5 (ddr2 667@cl5) s5 /s6 (ddr2 800@cl5&6) unit note idd0 1235 1280 1325 ma idd1 1325 1370 1415 ma idd2p 740 740 740 ma idd2q 893 920 938 ma idd2n 965 1010 1055 ma idd3p(f) 875 875 875 ma idd3p(s) 758 758 758 ma idd3n 1055 1100 1145 ma idd4r 1730 1910 2090 ma idd4w 1730 1955 2180 ma idd5b 2090 2135 2180 ma idd6 540 540 540 ma 1 idd7 2225 2405 2720 ma symbol c4 (ddr2 533@cl4) y5 (ddr2 667@cl5) s5 /s6 (ddr2 800@cl5&6) unit note idd0 1550 1640 1730 ma idd1 1640 1730 1820 ma idd2p 830 830 830 ma idd2q 1136 1190 1226 ma idd2n 1280 1370 1460 ma idd3p(f) 1100 1100 1100 ma idd3p(s) 866 866 866 ma idd3n 1460 1550 1640 ma idd4r 2045 2270 2495 ma idd4w 2045 2315 2585 ma idd5b 1405 2495 1585 ma idd6 630 630 630 ma 1 idd7 2675 2765 3125 ma
rev. 0.3 / oct. 2008 19 1 240pin registered ddr2 sdram dimms 2gb, 256m x 72 registered dimm : hmp125p7efr4c 4gb, 512m x 72 registered dimm : hmp151p7efr8c symbol c4 (ddr2 533@cl4) y5 (ddr2 667@cl5) s5 /s6 (ddr2 800@cl5&6) unit note idd0 1280 1910 2000 ma idd1 2000 2090 2180 ma idd2p 830 830 830 ma idd2q 1136 1190 1226 ma idd2n 1280 1370 1460 ma idd3p(f) 1100 1100 1100 ma idd3p(s) 866 866 866 ma idd3n 1460 1550 1640 ma idd4r 2810 3170 3530 ma idd4w 2810 3260 3710 ma idd5b 3330 3420 3510 ma idd6 630 630 630 ma 1 idd7 4070 4160 4790 ma symbol c4 (ddr2 533@cl4) y5 (ddr2 667@cl5) s5 /s6 (ddr2 800@cl5&6) unit note idd0 2180 2360 2540 ma idd1 2270 2450 2630 ma idd2p 690 690 690 ma idd2q 758 770 778 ma idd2n 790 810 830 ma idd3p(f) 750 750 750 ma idd3p(s) 698 698 698 ma idd3n 830 850 870 ma idd4r 2675 2290 3305 ma idd4w 2675 3035 3395 ma idd5b 5420 5780 6140 ma idd6 490 490 490 ma 1 idd7 3305 3485 3935 ma
rev. 0.3 / oct. 2008 20 1 240pin registered ddr2 sdram dimms 4gb, 512m x 72 registered dimm : hmp151p7efr4c 8gb, 1g x 72 registered dimm: hmp31gp7emr4c note : 1. idd6 current values are guaranteed up to tcase of 85c max. symbol c4 (ddr2 533@cl4) y5 (ddr2 667@cl5) s5 /s6 (ddr2 800@cl5&6) unit note idd0 2450 2630 2810 ma idd1 2630 2810 2990 ma idd2p 1010 1010 1010 ma idd2q 1622 1730 1802 ma idd2n 1910 2090 2270 ma idd3p(f) 1550 1550 1550 ma idd3p(s) 1082 1082 1082 ma idd3n 2270 2450 2630 ma idd4r 3440 3890 4340 ma idd4w 3440 3980 4520 ma idd5b 3960 4140 4320 ma idd6 810 810 810 ma 1 idd7 4430 4880 5600 ma symbol c4 (ddr2 533@cl4) y5 (ddr2 667@cl5) unit note idd0 3710 4070 ma idd1 3890 4250 ma idd2p 690 690 ma idd2q 758 770 ma idd2n 790 810 ma idd3p(f) 750 750 ma idd3p(s) 698 698 ma idd3n 830 850 ma idd4r 4700 5330 ma idd4w 4700 5420 ma idd5b 5220 5580 ma idd6 490 490 ma idd7 5690 6320 ma
rev. 0.3 / oct. 2008 21 1 240pin registered ddr2 sdram dimms idd measurement conditions note: 1. idd specifications ar e tested after the device is properly initialized 2. input slew rate is specified by ac parametric test condition 3. idd parameters are specified with odt disabled. 4. data bus consists of dq, dm, dqs, dqs , rdqs, rdqs , ldqs, ldqs, udqs, and udqs . idd values must be met with all combinations of emrs bits 10 and 11. 5. definitions for idd low is defined as vin vilac (max) high is defined as vin vihac (min) stable is defined as inputs stable at a high or low level floating is defined as inputs at vref = vddq/2 switching is defined as: inputs changing between high and low every other clock cycle (once pe r two clocks) for address and co n- trol signals, and inputs changing between high and low every other data transfer (once per clock) for dq signals not including masks or strobes symbol conditions units idd0 operating one bank active-precharge current ; t ck = t ck(idd), t rc = t rc(idd), t ras = t rasmin (idd);cke is high, cs is high between valid commands; addres s bus inputs are switching; data bus inputs are switching ma idd1 operating one bank active-read-precharge current ; iout = 0ma;bl = 4, cl = cl(idd), al = 0; t ck = t ck(idd), t rc = t rc (idd), t ras = t rasmin (idd), t rcd = t rcd(idd); cke is high, cs is high between valid commands; address bus inputs are sw itching; data pattern is same as idd4w ma idd2p precharge power-down current ; all banks idle; t ck = t ck(idd); cke is low; other control and address bus inputs are stable; data bus inputs are floating ma idd2q precharge quiet standby current ; all banks idle; t ck = t ck(idd);cke is high, cs is high; other control and address bus inputs are stable; data bus inputs are floating ma idd2n precharge standby current ; all banks idle; t ck = t ck(idd); cke is high, cs is high; other control and address bus inputs are switching; data bus inputs are switching ma idd3p active power-down current ; all banks open; t ck = t ck(idd); cke is low; other control and address bus inputs are stable; data bus inputs are floating fast pdn exit mrs(12) = 0 ma slow pdn exit mrs(12) = 1 ma idd3n active standby current ; all banks open; t ck = t ck(idd), t ras = t rasmax (idd), t rp = t rp(idd); cke is high, cs is high between valid commands; other control and address bus inputs are switching; data bus inputs are switching ma idd4w operating burst write current ; all banks open, continuous burst writes; bl = 4, cl = cl(idd), al = 0; t ck = t ck(idd), t ras = t rasmax (idd), t rp = t rp(idd); cke is high, cs is high between valid commands; address bus inputs are switching; data bus inputs are switching ma idd4r operating burst read current ; all banks open, continuous burst reads, iout = 0ma; bl = 4, cl = cl(idd), al = 0; t ck = t ck(idd), t ras = t rasmax (idd), t rp = t rp(idd); cke is high, cs is high between valid commands; address bus inputs are switchi ng; data pattern is same as idd4w ma idd5b burst refresh current ; t ck = t ck(idd); refresh command at every t rfc(idd) interval; cke is high, cs is high between valid commands; other control and addr ess bus inputs are switching; data bus inputs are switching ma idd6 self refresh current ; ck and ck at 0v; cke 0.2v; other control and address bus inputs are floating; data bus inputs are floating. idd6 current values are guaranted up to tcase of 85 ? max. ma idd7 operating bank interleave read current ; all bank interleaving reads, iout = 0ma; bl = 4, cl = cl(idd), al = t rcd(idd)-1* t ck(idd); t ck = t ck(idd), t rc = t rc(idd), t rrd = t rrd(idd), t rcd = 1* t ck(idd); cke is high, cs is high between valid commands; address bus inputs are stable during deselects; data pat- tern is same as idd4r; - refer to the following page for detailed timing conditions ma
rev. 0.3 / oct. 2008 22 1 240pin registered ddr2 sdram dimms electrical characteristics & ac timings speed bins and cl, tr cd, trp, trc and tras for corresponding bin ac timing parameters by speed grade (ddr2- 400 & ddr2-533) speed ddr2-800 (s5) ddr2-667 (y5) ddr2-533 (c4) unit bin (cl-trcd-trp) 5-5-5 5-5-5 4-4-4 parameter min min min cas latency 5 5 4ns trcd 12.5 15 15 ns trp 12.5 15 15 ns trc 57.5 60 60 ns tras 45 45 45 ns parameter symbol ddr2-400 ddr2-533 unit note min max min max data-out edge to clock edge skew tac -600 600 -500 500 ps dqs-out edge to clock edge skew tdqsck -500 500 -500 450 ns clock high level width tch 0.45 0.55 0.45 0.55 ck clock low level width tcl 0.45 0.55 0.45 0.55 ck clock half period thp min (tcl, tch) - min (tcl, tch) -ns system clock cycle time tck 5000 8000 3750 8000 ps dq and dm input setup time tds 150 - 100 - ps 1 dq and dm input hold time tdh 275 - 225 - ps 1 control & address input pulse width for each input tipw 0.6 - 0.6 - tck dq and dm input pulse width for each input pulse width for each input tdipw 0.35 - 0.35 - tck data-out high-impedance window from ck, /ck thz - tac max - tac max ps dqs low-impedance time from ck/ck tlz(dqs) tac min tac max tac min tac max ps dq low-impedance time from ck/ck tlz(dq) 2*tac min tac max 2*tac min tac max ps dqs-dq skew for dqs and associated dq signals tdqsq - 350 -300 ps dq hold skew factor tqhs - 450 -400 ps dq/dqs output hold time from dqs tqh thp - tqhs - thp - tqhs - ps write command to first dqs latching transition tdqss wl - 0.25 wl + 0.25 wl - 0.25 wl + 0.25 tck dqs input high pulse width tdqsh 0.35 - 0.35 - tck dqs input low pulse width tdqsl 0.35 - 0.35 - tck dqs falling edge to ck setup time tdss 0.2 - 0.2 - tck dqs falling edge hold time from ck tdsh 0.2 - 0.2 - tck mode register set command cycle time tmrd 2 - 2 - tck write preamble twpre 0.35 - 0.35 - tck
rev. 0.3 / oct. 2008 23 1 240pin registered ddr2 sdram dimms note: 1. for details and notes, please refer to the relevant hynix component datasheet h5ps1g[4,8]3efr. 2. 0 c ? t case ? 85 c 85 c # t case ? 95 c write postamble twpst 0.4 0.6 0.4 0.6 tck address and control input setup time tis 350 - 250 - ps address and control input hold time tih 475 - 375 - ps read preamble trpre 0.9 1.1 0.9 1.1 tck read postamble trpst 0.4 0.6 0.4 0.6 tck auto-refresh to active/auto-refresh command period trfc 127.5 - 127.5 - ns row active to row active delay for 1kb page size trrd 7.5 - 7.5 - ns row active to row active delay for 2kb page size trrd 10 - 10 - ns four activate window for 1kb page size tfaw 37.5 - 37.5 - ns four activate window for 2kb page size tfaw 50 - 50 - ns cas to cas command delay tccd 2 2 tck write recovery time twr 15 -15 - ns auto precharge write recovery + precharge time tdal twr + trp - twr + trp - tck write to read command delay twtr 10 - 7.5 - ns internal read to precharge command delay trtp 7.5 7.5 ns exit self refresh to a non-read command txsnr trfc + 10 trfc + 10 ns exit self refresh to a read command txsrd 200 - 200 - tck exit precharge power down to any non-read command txp 2 - 2 - tck exit active power down to read command txard 2 2 tck exit active power down to read command (slow exit, lower power) txards 6 - al 6 - al tck cke minimum pulse width (high and low pulse width) tcke 3 3 tck odt turn-on delay taond 2 2 2 2 tck odt turn-on taon tac (min) tac(max)+1 tac (min) tac(max)+1 ns odt turn-on (power-down mode) taonpd tac(min)+2 2tck+tac(m ax)+1 tac(min)+2 2tck+tac(m ax)+1 ns odt turn-off delay taofd 2.5 2.5 2.5 2.5 tck odt turn-off taof tac (min) tac (max)+ 0.6 tac (min) tac (max)+ 0.6 ns odt turn-off (power-down mode) taofpd tac(min)+2 2.5tck+tac( max)+1 tac(min)+2 2.5tck+tac( max)+1 ns odt to power down entry latency tanpd 3 3 tck odt power down exit latency taxpd 8 8 tck ocd drive mode output delay toit 0 12 0 12 ns minimum time clocks remains on after cke asynchronously drops low tdelay tis + tck + tih tis + tck + tih ns average periodic refresh interval trefi - 7.8 - 7.8 us 2 trefi - 3.9 - 3.9 us 3 parameter symbol ddr2-400 ddr2-533 unit note min max min max
rev. 0.3 / oct. 2008 24 1 240pin registered ddr2 sdram dimms (ddr2-667 & ddr2-800) parameter symbol ddr2-667 ddr2-800 unit note min max min max dq output access time from ck/ck tac -450 +450 -400 +400 ps dqs output access time from ck/ck tdqsck -400 +400 -350 +350 ps ck high-level width tch 0.45 0.55 0.45 0.55 tck ck low-level width tcl 0.45 0.55 0.45 0.55 tck ck half period thp min(tcl, tch) - min(tcl, tch) - ps clock cycle time, cl=x tck 3000 8000 2500 ps dq and dm input setup time (differential strobe) tds 100 - 50 - ps 1 dq and dm input hold time (differential strobe) tdh 175 - 125 - ps 1 control & address input pulse width for each input tipw 0.6 - 0.6 - tck dq and dm input pulse width for each input tdipw 0.35 - 0.35 - tck data-out high-impedance time from ck/ck thz - tac max - tac max ps dqs low-impedance time from ck/ck tlz(dqs) tac min tac max tac min tac max ps dq low-impedance time from ck/ck tlz(dq) 2*tac min tac max 2*tac min tac max ps dqs-dq skew for dqs and associated dq signals tdqsq - 240 -200 ps dq hold skew factor tqhs - 340 -300 ps dq/dqs output hold time from dqs tqh thp - tqhs - thp - tqhs - ps first dqs latching transition to associated clock edge tdqss - 0.25 + 0.25 - 0.25 + 0.25 tck dqs input high pulse width tdqsh 0.35 - 0.35 - tck dqs input low pulse width tdqsl 0.35 - 0.35 - tck dqs falling edge to ck setup time tdss 0.2 - 0.2 - tck dqs falling edge hold time from ck tdsh 0.2 - 0.2 - tck mode register set command cycle time tmrd 2 - 2 - tck write preamble twpre 0.35 - 0.35 - tck write postamble twpst 0.4 0.6 0.4 0.6 tck auto-refresh to active/auto-refresh command period trfc 127.5 - 127.5 - ns row active to row active delay for 1kb page size trrd7.5-7.5-ns address and control input setup time tis 200 -175 - ps address and control input hold time tih 275 -250 - ps read preamble trpre 0.9 1.1 0.9 1.1 tck read postamble trpst 0.4 0.6 0.4 0.6 tck activate to precharge command tras 45 70000 45 70000 ns active to active command period for 1kb page size products trrd 7.5 -7.5 - ns row active to row active delay for 2kb page size trrd 10 - 10 - ns four active window for 1kb page size products tfaw 37.5 - 35 - ns four activate window for 2kb page size tfaw 50 - 50 - ns cas to cas command delay tccd 2 2 tck write recovery time twr 15 -15 - ns auto precharge write recovery + precharge time tdal wr+trp - wr+trp - tck internal write to read command delay twtr 7.5 -7.5 - ns internal read to precharge command delay trtp 7.5 7.5 ns
rev. 0.3 / oct. 2008 25 1 240pin registered ddr2 sdram dimms note: 1. for details and notes, please refer to the relevant hynix component datasheet h5ps1g[4,8]3efr. 2. 0 c ? t case ? c c # t case ? c parameter symbol ddr2-667 ddr2-800 unit note min max min max exit self refresh to a non-read command txsnr trfc + 10 trfc + 10 ns exit self refresh to a read command txsrd 200 - 200 - tck exit precharge power down to any non-read command txp 2 - 2 - tck exit active power down to read command txard 2 2 tck exit active power down to read command (slow exit, lower power) txards 7 - al 8 - al tck cke minimum pulse width (high and low pulse width) tcke 3 3 tck odt turn-on delay taond 2 2 2 2 tck odt turn-on taon tac (min) tac (max) +0.7 tac (min) tac (max) +0.7 ns odt turn-on (power-down mode) taonpd tac(min)+2 2tck+ tac(max)+1 tac (min) +2 2tck+ tac(max)+1 ns odt turn-off delay taofd 2.5 2.5 2.5 2.5 tck odt turn-off taof tac (min) tac (max)+ 0.6 tac (min) tac (max) +0.6 ns odt turn-off (power-down mode) taofpd tac (min) +2 2.5tck+ tac(max)+1 tac (min) +2 2.5tck+ tac(max)+1 ns odt to power down entry latency tanpd 3 3 tck odt power down exit latency taxpd 8 8 tck ocd drive mode output delay toit 0 12 0 12 ns minimum time clocks remains on after cke asynchronously drops low tdelay tis + tck + tih tis + tck + tih ns average periodic refresh interval trefi - 7.8 - 7.8 us 2 trefi - 3.9 - 3.9 us 3
rev. 0.3 / oct. 2008 26 1 240pin registered ddr2 sdram dimms package outline 128mx72 (1 rank) - hmp112p7efr8c register 55.0 63.0 5.0 2x 3.00min front 1.27 ? 0.10 2.70max side 1.0 0.35 0.8 ? 0.05 2.50 ? 0.20 detail of contacts a note) all dimensions are typi cal unless otherwise stated. inches millimeters 4x full r detail-a detail-b 128.95 133.35 2x ?? 0.10 4x 4.0 ? 0.1 2x 2.3 ? 0.1 5.175 2x r1.00 10.00 17.80 30.00 0.05 back pll 5.00 1.50 ? 0.10 3.80 2.50 detail of contacts b 3.0 ? 0.15 0.3 ? 0.7
rev. 0.3 / oct. 2008 27 1 240pin registered ddr2 sdram dimms package outline 256mx72 (2 rank) - hmp125p7efr8c 55.0 63.0 5.0 2x 3.00min front 1.27 ? 0.10 4.00max side 1.0 0.35 0.8 ? 0.05 2.50 ? 0.20 5.00 1.50 ? 0.10 3.80 2.50 detail of contacts a detail of contacts b note) all dimensions are typi cal unless otherwise stated. inches millimeters 4x full r detail-a detail-b 128.95 133.35 2x ?? 0.10 4x 4.0 ? 0.1 2x 2.3 ? 0.1 5.175 2x r1.00 10.00 17.80 30.00 0.05 back 3.0 ? 0.15 0.3 ? 0.7 register pll register
rev. 0.3 / oct. 2008 28 1 240pin registered ddr2 sdram dimms package outline 256mx72 (1 rank) - hmp125p7efr4c 55.0 63.0 5.0 2x 3.00min front 1.27 ? 0.10 4.00max side 1.0 0.35 0.8 ? 0.05 2.50 ? 0.20 5.00 1.50 ? 0.10 3.80 2.50 detail of contacts a detail of contacts b note) all dimensions are typi cal unless otherwise stated. inches millimeters 4x full r detail-a detail-b 128.95 133.35 2x ?? 0.10 4x 4.0 ? 0.1 2x 2.3 ? 0.1 5.175 2x r1.00 10.00 17.80 30.00 0.05 back 3.0 ? 0.15 0.3 ? 0.7 register pll register
rev. 0.3 / oct. 2008 29 1 240pin registered ddr2 sdram dimms package outline 512mx72 (4 ranks) - hymp151p7efr8c 55.0 63.0 5.0 2x 3.00min front 1.27 ? 0.10 4.00max side 1.0 0.35 0.8 ? 0.05 2.50 ? 0.20 detail of contacts a note) all dimensions are typi cal unless otherwise stated. inches millimeters 4x full r detail-a detail-b 128.95 133.35 2x ?? 0.10 4x 4.0 ? 0.1 2x 2.3 ? 0.1 5.175 2x r1.00 10.00 17.80 30.00 0.05 back register pll register 5.00 1.50 ? 0.10 3.80 2.50 detail of contacts b 3.0 ? 0.15 0.3 ? 0.7 register register
rev. 0.3 / oct. 2008 30 1 240pin registered ddr2 sdram dimms package outline 512mx72 (2 ranks) - hymp151p7efr4c 55.0 63.0 5.0 2x 3.00min front 1.27 ? 0.10 4.00max side 1.0 0.35 0.8 ? 0.05 2.50 ? 0.20 detail of contacts a note) all dimensions are typi cal unless otherwise stated. inches millimeters 4x full r detail-a detail-b 128.95 133.35 2x ?? 0.10 4x 4.0 ? 0.1 2x 2.3 ? 0.1 5.175 2x r1.00 10.00 17.80 30.00 0.05 back register pll 5.00 1.50 ? 0.10 3.80 2.50 detail of contacts b 3.0 ? 0.15 0.3 ? 0.7 register
rev. 0.3 / oct. 2008 31 1 240pin registered ddr2 sdram dimms package outline 1gx72 (4 ranks) - hmp31gp7emr4c register pll 55.0 63.0 5.0 2x 3.00min front 1.27 ? 0.10 7.55max side 1.0 0.35 0.8 ? 0.05 2.50 ? 0.20 detail of contacts a note) all dimensions are typi cal unless otherwise stated. inches millimeters 4x full r detail-a detail-b 128.95 133.35 2x ?? 0.10 4x 4.0 ? 0.1 2x 2.3 ? 0.1 5.175 2x r1.00 10.00 17.80 30.00 register 0.05 back 5.00 1.50 ? 0.10 3.80 2.50 detail of contacts b 3.0 ? 0.15 0.3 ? 0.7
rev. 0.3 / oct. 2008 32 1 240pin registered ddr2 sdram dimms revision history revision history date 0.1 initial release jul. 2008 0.2 editorial correction sep. 2008 0.3 added 2rx8, 4rx8 oct. 2008

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